As CMOS technology grows, more effort has been made in the research of successive approximation analog-to-digital converters. As to conventional successive approximation analog-to-digital converters, capacitors in the capacitor array are designed by using binary increment which features easily reconfiguration and where the output of capacitors is the result of analog-to-digital converters.
Technically, analog-to-digital converters are packaged in an IC chip, where the circuit layout must be designed in a rigorous and orderly way due to binary increment (powers of 2). The conventional one, lack of flexibility in layout design, is unable to achieve the tradeoff between speed and size because of the rigorous capacitor array. Therefore, it can not meet the requirement of high speed low power successive approximation analog-to-digital converters.
So, the capacitor array arrays in analog-to-digital converters are in need for improvement to fit in the high resolution low power technology.